As is well known, a solid state storage device is a data storage device that uses a NAND-based flash memory to store data. The NAND-based flash memory is a non-volatile memory. After data are written to the flash memory, if the system is powered off, the data are still retained in the flash memory.
Generally, each cell of the flash memory has a floating gate transistor. During a program cycle of the flash memory, hot carriers are injected into the floating gate of the floating gate transistor. By controlling the amount of hot carriers to be injected into the floating gate, the threshold voltage of the floating gate transistor can be changed. Consequently, the storing state of the cell is determined according to the threshold voltage. During an erase cycle, the hot carriers are ejected from the floating gate of the floating gate transistor.
Depending on different designs, the flash memories may be classified into several types, including single-level cell flash memories and multi-level cell flash memories. The multi-level cell flash memories include double-level cell flash memories, triple-level cell flash memories or more-level cell flash memories.
FIG. 1 schematically illustrates the threshold voltage distribution curves of the various flash memories in different storing states. The single-level cell flash memory can store only one bit of data per cell (i.e., 1 bit/cell). According to the amount of the hot carriers injected into the cell, there are two storing states of each cell of the single-level cell flash memory corresponding to two threshold voltage distribution curves. For example, the cell with the lower threshold voltage is the storing state “0”, and the cell with the higher threshold voltage is the storing state “1”. The storing state “0” and the storing state “1” are two different storing states. Moreover, the storing state “0” is also indicated as a first storing state, and the storing state “1” is also indicated as a second storing state. For example, the cell with the threshold voltage of approximately 0V is the first storing state, and the cell with the threshold voltage of approximately 10V is the second storing state.
The double-level cell flash memory can store two bits of data per cell (i.e., 2 bits/cell). According to the amount of the hot carriers injected into the cell, each cell of the double-level cell flash memory has four storing states corresponding to four threshold voltage distribution curves. According to the threshold voltages in ascending order, the storing states of the cells include the storing state “00”, the storing state “01”, the storing state “10” and the storing state “11”.
The triple-level cell flash memory can store three bits of data per cell (i.e., 3 bits/cell). According to the amount of the hot carriers injected into the cell, each cell of the triple-level cell flash memory has eight storing states corresponding to eight threshold voltage distribution curves. According to the threshold voltages in ascending order, the storing states of the cells include the storing state “000”, the storing state “001”, the storing state “010”, the storing state “011”, the storing state “100”, the storing state “101”, the storing state “110” and the storing state “111”.
That is, during the program cycle of the flash memory, the threshold voltage and the storing state of the cell are correspondingly changed by controlling the amount of the hot carriers injected into the cell. For programming the single-level cell flash memory, a single program procedure is required to program the cells to the desired storing states. However, for programming the multi-level cell flash memory, many program procedures are required to program the cells to the desired storing states.
FIG. 2A schematically illustrates an approach of programming a double-level cell flash memory. In FIG. 2A, two program procedures are performed to program the cell of the double-level cell flash memory to the storing state “10”. Firstly, in the first program procedure, the cell is programmed to the storing state “11” in response to a first program voltage. Then, in the second program procedure, the cell is programmed to the storing state “10” in response to a second program voltage.
Similarly, for programming the cell of the double-level cell flash memory to the storing state “01”, the cell is programmed to the storing state “00” in the first program procedure, and the cell is programmed to the storing state “01” in the second program procedure.
Generally, the flash memory comprises plural blocks. Each block contains plural pages. During the program cycle, data are written into at least one page of the flash memory. The size of the page is defined by the manufacturer of the flash memory. For example, the size of each page is 2K bytes, 4K bytes or 8K bytes. For example, the write data of the 4K bytes page contain user data, encoding data and associated data and have a total of 4224 bytes (=4224×8 bits).
In other words, a total of 4224×8 cells of the single-level cell flash memory are required to store the data of a 4K bytes page. Since the data density of the double-level cell flash memory is higher, a total of 4224×8 cells of the double-level cell flash memory can store two pages of data (=2×4224 bytes). Similarly, a total of 4224×8 cells of the triple-level cell flash memory can store three pages of data (=3×4224 bytes).
FIGS. 2B and 2C schematically illustrate the uses of 4224×8 double-level cells of the flash memory to store two pages of data. Take the first byte (Byte-1) as an example. During the program cycle, the write data 0x65h (001100101b) is stored in the first byte of the page M, and the write data 0xDBh (11011011b) is stored in the first byte of the page N.
Please refer to FIG. 2B. In the first program procedure, the write data (01100101b) of the first byte of the page M is programmed to eight cells of the flash memory. Consequently, the storing states of the eight cells are “00”, “11”, “11”, “00”, “00”, “11”, “00” and “11”, respectively. After the first program procedure, the write data of the first byte of the page M is 01100101b, and the write data of the first byte of the page N is also 01100101b.
Please refer to FIG. 2C. In the second program procedure, the write data (11011011b) of the first byte of the page N is programmed to eight cells of the flash memory. Consequently, the storing states of the eight cells are changed to “01”, “11”, “10”, “01”, “01”, “10”, “01” and “11”, respectively. After the second program procedure, the write data of the first byte of the page M is 01100101b, and the write data of the first byte of the page N becomes 11011011b.
In other words, after the first program procedure, the 4224×8 cells can only store the data of the page M. After the second program procedure, the 4224×8 cells can store the data of the page M page and the data of the page N.
According to the specifications of the multi-level cell flash memories, the double-level cell flash memory comprises upper pages and lower pages. The page M of FIG. 2B is one of the upper pages, and the page N of FIG. 2C is one of the lower pages. In other words, the first program procedure is an upper page program procedure, and the second program procedure is a lower page program procedure. After both of the upper page program procedure and the lower page program procedure are completed, the data of the double-level cell flash memory can be read.
Similarly, the triple-level cell flash memory comprises upper pages, middle pages and lower pages. During the program cycle, three program procedures are required to program the upper page, the middle page and the lower page, respectively.
However, according to the specifications of the triple-level cell flash memory, the same three-level cells cannot be programmed by three consecutive program procedures. Consequently, the triple-level cell flash memory has the risk of losing data during the program cycle.